1. Field of the Invention
The present invention relates to a method and apparatus for preventing P1 punchthrough by using a film that is highly selective to P1 with respect to a particular etch chemical used. In particular, the present invention relates to a method and apparatus for providing a good contact to a first polysilicon layer formed on a semiconductor substrate.
2. Description of the Related Art
When constructing a RAM or ROM cell using a semiconductor substrate, metal contacts must be provided to each layer formed on the substrate. For example, a metal-oxide-semiconductor (MOS) transistor formed on the semiconductor substrate has a gate region, a source region, and a drain region. A metal contact must be provided to each of these regions, so that the appropriate voltage and/or current can be supplied to the gate, source and drain of the MOS transistor.
Given the small size of such devices, there is not much leeway in providing such contacts, and any errors in this process may lead to defective components. For example, an etch to a particular layer may be performed for too long a period of time, thereby etching through a desired layer to be contacted with, and instead contacting with another layer that has a different function than the desired layer.
FIGS. 1A-1H show a conventional process for creating a RAM memory cell on a semiconductor substrate. In a first step, as shown in FIG. 1A, a thin layer of insulator is formed over the silicon substrate 10. This insulator layer 12 may conveniently comprise a thermally grown SiO.sub.3, and is typically referred to as a pad oxide layer. As shown in FIG. 1A, another insulator layer is formed over the insulator layer 12, and serves as a second insulator layer 14 that functions as an oxidation mask. By way of example, this second different insulator layer 14 may comprise a nitride layer formed by means of a chemical vapor deposition (CVD) process.
Referring now to FIG. 1B, the semiconductor structure is shown with a patterned photo-resist layer 16 formed thereon. The resist pattern is used to protect the areas where active devices will be formed. This patterning may be accomplished by means of standard lithography and etching techniques that are well known in the art.
Referring now to FIG. 1C, the semiconductor structure is shown after an etching step and a photo-resist clean step. The etching step operates to remove all of the nitride layer 14 that is exposed, i.e., that is not covered or protected by the photo-resist pattern 16 of FIG. 1B.
Referring now to FIG. 1D, a field oxide region 18 is grown, by way of example, by a thermal growth process using wet oxidation, in the exposed areas of the layer 12, i.e., those areas of the layer 12 which are not covered by the nitride pattern 14. A typical field oxide region may rise above the surface of the surrounding semiconductor area by about 1000 to 4000 angstroms. The field oxide region 18 provide isolation between separate components (i.e., transistors) formed on the same semiconductor substrate.
Referring now to FIG. 1E, the nitride pattern 14 is removed by means of a nitride clean step, and a thin tunnel oxide layer 20 is formed over the semiconductor substrate including the field oxide region 18. This thin oxide layer 20 may be formed utilizing standard thermal growth techniques in an oxidation ambient. In a preferred embodiment, this oxide layer 20 may be on the order of 100 angstroms. Following the formation of this oxide layer 20, a conductive polysilicon layer 22 is deposited thereover, by way of example, by a CVD process. The polysilicon layer (P1 layer) 22 may be amorphous polysilicon and may include doping, or doping may be added after deposition to provide a desired conductivity. A typical conductivity for the P1 layer 22, which is set forth by way of example, and not by way of limitation, is 400 ohms per square. The P1 layer 22 typically will be deposited to a thickness on the order of 500-1000 angstroms. The P1 layer 22 corresponds to a layer that stores electrons, such as for storing a binary "1" value for a RAM memory cell. The electrons can be removed from the P1 layer 22, thereby erasing the RAM cell (i.e., creating a "0" value in the RAM memory cell).
The polysilicon layer deposition step is then followed by an etching step to form openings 24 through the P1 layer 22 down to the field oxide layer 18. In a preferred embodiment, these openings are formed by directionally etching the top surface of the doped P1 layer 22 after masking, using standard photo-lithographic techniques. Such photo-lithographic masking techniques are well known in the art and include, by way of example, disposing an insulator of SiO.sub.2 or some other etch-resistant material on the top surface of the material to be etched. This SiO.sub.2 layer may be deposited or grown by any known means in the art, such as by oxidizing the P1 layer 22 in steam or in wet oxygen. A portion of the insulating layer of SiO.sub.2 is removed using a photo-resist layer selectively exposed to UV radiation and then developed chemically to act as a mask for the SiO.sub.2. The masked SiO.sub.2 may then be etched with a buffered hydrofluoric acid solution, for example, leaving a remaining portion of the SiO.sub.2 layer above the polysilicon surface in a desired pattern. Then, a directional etch is utilized to form trenches with vertical sidewalls in areas of polysilicon not covered by the patterned SiO.sub.2 mask. Typical chemical directional etches are SF.sub.6 CCLF.sub.2 in a plasma-form. The etching process is performed for a particular period of time based on the thickness of the layer-to-be-etched, and any deviation from that time may result in too little etching or too much etching. Other variables that enter into the etching process are the particular environmental conditions that exist during the etch, which should be maintained in a fairly precise range. The result of the directional etching process are openings having sidewalls that are substantially vertical.
Referring now to FIG. 1F, the semiconductor structure is shown after an ONO process and the deposition of a second layer of polysilicon. Specifically, the ONO layer 26 may be formed, by way of example, by forming a first layer of oxide by means of a thermal growth process, forming a second layer of nitride by means of chemical vapor deposition, and forming a third layer of oxide by means of chemical vapor deposition. By way of example, but not by way of limitation, this layer 26 may be on the order of 160 angstroms.
Following the deposition of ONO isolation layer 26, a second layer of polysilicon (P2 layer) 28 is deposited in a well-known manner, such as by a CVD process. The P2 layer 28 may have a thickness on the order of 1200 angstroms. The P2 layer 28 should have a higher doping level than the P1 layer 22. This doping to obtain the desired conductivity may be accomplished during the layer deposition phase or after the deposition of the polysilicon layer. The P2 layer 22 corresponds to a control gate, and when a particular voltage is applied to the P2 layer 22, electrons are either supplied to the P1 layer 22 or removed from the P1 layer 22. Thus, the P2 layer 22 may be used to program a memory cell when the semiconductor device is configured as a RAM.
After the P2 layer 28 is formed on the substrate, an etching process is performed to provide "holes" through which contacts may be made to lower layers on the substrate, such as the P1 layer 22. For example, the techniques described above with respect to patterning the P1 layer 22 may be utilized to pattern the P2 layer 28 so as to form openings to provide contact regions to lower level layers (such as the P1 layer 22). Such a formation of holes in the P2 layer 28 is needed when the P1 layer and the P2 layer 28 are in a same direction (i.e., in a plane going into the paper in FIGS. 1A-1H), and is generally not needed when the P1 layer 22 and the P2 layer 28 are formed in different directions (i.e. direction of P1 layer 22 perpendicular to P2 layer 28).
After the P2 layer 28 has been deposited onto the semiconductor structure and patterned (and after any doping has been applied to that second layer of polysilicon 28), a metal silicide layer, for example, WSi.sub.x (x=2 or 4), is deposited onto the semiconductor structure, for example, with silane gas. Other types of metals, such as tantalum, palladium, molybdenum, may be utilized instead of tungsten, as is known to those of ordinary skill in the art. As shown in FIG. 1G, the metal silicide layer 33 and the P2 layer 28 are patterned via standard lithography techniques to form openings 40 so as to provide contact regions to lower layers, such as to the P2 layer 28, the P1 layer 22, and to the silicon substrate itself. During the patterning of the P2 layer 28, portions of the ONO isolation layer 26 underneath the patterned P2 layer 28 will also be etched away. The patterning of the P1 layer 22 and the P2 layer 28 is such that there are provided openings in the P2 layer 28 to provide a contact region to the P1 layer 22, and there are provided openings in both the P1 layer 22 and the P2 layer 28 that are coplanar so as to provide a contact region to the silicon substrate.
Thereafter, an interlayer dielectric (ILD) 38 is deposited onto the semiconductor structure. After the ILD layer 38 is deposited, it is polished to a substantially uniform thickness. For example, the ILD layer 38 may be polished to a thickness of approximately 1.1 microns. Afterwards, a dry plasma etch is utilized to pattern the ILD layer 38 so as to form openings 50A, 50B and 50C in the ILD layer 38 so as to provide contact regions to lower layers on the semiconductor substrate, as shown in FIG. 1H. Such a dry plasma etch may involve, for example, using a photoresist and placing the semiconductor substrate in a mixed gas environment using C.sub.4 F.sub.8 and O.sub.2, to thereby etch away portions of the oxide where desired.
For a RAM device, a word line is provided to the P2 layer, via a metal contact. Also, a word select line is provided to the P1 layer, via another metal contact. Both metal contacts must be applied to the correct layer on the substrate, requiring a fairly accurate etching process to reach the appropriate layer on the substrate. For example, when etching down to the P1 layer, it is possible that the etch may go too far, thereby etching all the way through the P1 layer and to the semiconductor substrate itself. This "P1 punchthrough" is highly undesirable, and leads to a defective device.
It is preferable to etch to the top surface of the P1 layer, to provide a best possible contact point to that layer. However, the etching process may be such that the etch is made to a middle location in the P1 layer, thereby not providing the best possible metal contact point to that layer.
Therefore, it is desirable to construct a semiconductor device that allows for fairly accurate etching to the appropriate layer, so as to provide strong and stable metal contact points to the P1 layer.